<?xml version='1.0' encoding='UTF-8'?>
<?xml-stylesheet href="/static/style.xsl" type="text/xsl"?>
<rss xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/" version="2.0">
  <channel>
    <title>Most recent entries from all</title>
    <link>https://cve.radiocsirt.org</link>
    <description>Contains only the most 10 recent entries.</description>
    <docs>http://www.rssboard.org/rss-specification</docs>
    <generator>python-feedgen</generator>
    <language>en</language>
    <lastBuildDate>Tue, 06 Oct 2026 08:42:40 +0000</lastBuildDate>
    <item>
      <title>CVE-2023-34326 — x86/AMD: missing IOMMU TLB flushing</title>
      <link>https://cve.radiocsirt.org/vuln/cve-2023-34326</link>
      <description>&lt;p&gt;&lt;strong&gt;Affected:&lt;/strong&gt; Xen&lt;/p&gt;
&lt;p&gt;The caching invalidation guidelines from the AMD-Vi specification (48882—Rev
3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction
(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU
TLB is not flushed.&lt;/p&gt;
&lt;p&gt;Such stale DMA mappings can point to memory ranges not owned by the guest, thus
allowing access to unindented memory regions.&lt;/p&gt;</description>
      <content:encoded>&lt;p&gt;&lt;strong&gt;Affected:&lt;/strong&gt; Xen&lt;/p&gt;
&lt;p&gt;The caching invalidation guidelines from the AMD-Vi specification (48882—Rev
3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction
(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU
TLB is not flushed.&lt;/p&gt;
&lt;p&gt;Such stale DMA mappings can point to memory ranges not owned by the guest, thus
allowing access to unindented memory regions.&lt;/p&gt;</content:encoded>
      <guid isPermaLink="false">https://cve.radiocsirt.org/vuln/cve-2023-34326</guid>
    </item>
  </channel>
</rss>
