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  <updated>2026-10-06T23:04:31.843433+00:00</updated>
  <author>
    <name>Vulnerability-Lookup</name>
    <email>csirt@opendfir.org</email>
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  <entry>
    <id>https://cve.radiocsirt.org/vuln/cve-2023-46835</id>
    <title>CVE-2023-46835 — x86/AMD: mismatch in IOMMU quarantine page table levels</title>
    <updated>2026-10-06T23:04:31.859266+00:00</updated>
    <content type="xhtml">
      <div xmlns="http://www.w3.org/1999/xhtml"><p><strong>Affected:</strong> Xen</p>
<p>The current setup of the quarantine page tables assumes that the
quarantine domain (dom_io) has been initialized with an address width
of DEFAULT_DOMAIN_ADDRESS_WIDTH (48) and hence 4 page table levels.</p>
<p>However dom_io being a PV domain gets the AMD-Vi IOMMU page tables
levels based on the maximum (hot pluggable) RAM address, and hence on
systems with no RAM above the 512GB mark only 3 page-table levels are
configured in the IOMMU.</p>
<p>On systems without RAM above the 512GB boundary
amd_iommu_quarantine_init() will setup page tables for the scratch
page with 4 levels, while the IOMMU will be configured to use 3 levels
only, resulting in the last page table directory (PDE) effectively
becoming a page table entry (PTE), and hence a device in quarantine
mode gaining write access to the page destined to be a PDE.</p>
<p>Due to this page table level mismatch, the sink page the device gets
read/write access to is no longer cleared between device assignment,
possibly leading to data leaks.</p></div>
    </content>
    <link href="https://cve.radiocsirt.org/vuln/cve-2023-46835"/>
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